Abnormality Detection of ECG Signals using Partial Reconfiguration in FPGA

Reconfigurable hardware is a potential technique, which improves the performance of the systems being implemented in it. In this paper, the implementation of an ECG system for detection of abnormalities in real time has been considered using the Partial Reconfiguration technique. The implementation has been done in the Virtex-5 FPGA hardware using Verilog HDL. The performance of the implemented system has been compared with the conventional hardware. The results show that reconfiguration time of partial reconfiguration takes only 1.901 ns whereas conventional one takes 6.04 ns to detect the abnormalities in the ECG signal. The Processing Speed of the Partial Reconfiguration is three times better than the Conventional method.